CXD1968AR
SYR_STAT
Read Only
Offset Address: 0x12
Bit
Name
Description
Default R/W
7:6 Reserved
—
—
R
R
5
4
3
2
TEST5
SYR locked indication (guard detection and
symbol position determined)
SYR Locked
Reserved
SYR Mode
—
—
—
R
R
R
0: 2K
1: 8K
SYR detected mode
00: 1/32
01: 1/16
10: 1/8
11: 1/4
1:0 SYR Guard
SYR detected guard interval
—
R
FFT_CTL
Read/Write
Description
RESET: 0x00
Default R/W
Offset Address: 0x17
Bit
Name
7:3 Reserved
00h
R/W
A “0” to “1” transition causes the FFT to be triggered to perform
an FFT on its current input buffer. Software should write “1”
then “0” to this bit.
2
FFT Test Trigger
0
R/W
1
0
FFT Manual Mode Set to disable FFT input buffer filling with off-air data.
0
0
R/W
R/W
FFT Inverse
Transform
Inverse FFT selection. Set to “0” for normal OFDM
demodulation.
SCR_CTL
Read/Write
Description
RESET: 0x30
Default R/W
Offset Address: 0x18
Bit
7
Name
Reserved
0
R/W
000: 1
001: 1/2
010: 1/4
011: 1/8
100: 1/16
101: 1/32
110: 1/64
111: 1/128
6:4 SYR Adjust Decay
3:2 Reserved
These bits are not used in the CXD1968AR.
011
R/W
00
0
R/W
R/W
SCR No Common
1
Set to disable common phase error correction.
Phase
Set to disable carrier phase slope correction. Note that this is
not compatible with SYR tracking, so SYR_CTL (SYR
Tracking Disable) must also be set.
0
SCR Disable
0
R/W
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SONY [ SONY CORPORATION ]
