CXD1968AR
CAS_CTL
Read/Write
RESET: 0x14
Default R/W
Offset Address: 0x0E
Bit
7
Name
Description
Enable co-channel interference suppression (CCS)
continuously within the CAS block. The CCS is off by
default during normal operation, but is enabled
automatically if CCI is detected regardless of the setting of
this bit.
CCS Enable
0
0
R/W
R/W
Disable first stage of adjacent channel interference
suppression within the CAS block. The first stage of ACS
is on by default. The second stage can be enabled by
CAS_CTRL_2 register for increased ACI rejection in 1 SAW
tuner designs.
6
5
ACS Disable
Disable the digital AGC within the CAS block. The digital
AGC is on by default
DAGC Disable
0
R/W
R/W
00: No reduction
Reduce DAGC BW
01: Reduce BW by 2
once the SYR has
10: Reduce BW by 4 (default)
locked.
4:3 DAGCBW Reduction
2:0 CCSMU
10
11: Reduce BW by 8
Set the BW of the co-channel suppression filter. A large
value corresponds to wide BW and vice versa. The reset
value of 4 gives good performance for PAL interference.
100
R/W
Note) This diagram illustrates the selection logic for control of the CCI filter.
I2C CAS_CTL
CCS_Enable
Bit-7
(CCS_Enable)
I2C CAS_CTRL_2
Bit-1
(CCS_State)
Enhanced
Symbol
CCI Detected
Tracking Block
Incoming
Samples
Filtered
Samples
CCI
Rejection
Circuit
- 54 -
SONY [ SONY CORPORATION ]
