CXD1968AR
Name
Addr. R/W
7
6
5
4
3
2
1
0
93
94
R
R
VBER[7:0]
VBER[15:8]
VIT_BER
Miscellaneous Registers
CHIP_INFO
A0
R
CHIP Identification
Version
RST_REG
A2 R/W
A3 R/W
Adc rst
Ts if int
Cofdm rst
Cofdm Int
Vit rst
Fec rst
Reserved
Hard
Cold
Warm
Ts synch
Lock
Rs Cwrjct
Flag
INTERRUPT_SOURCE
INTERRUPT_MASK
Ts Llck Flag Reserved
Ber_Es
Ber_Ses
Cofdm Int
En
Ts Llck Flag
Rs Cwrjct
Flag En
A4 R/W Ts if int en
Ts Synch
Reserved Ber_Es En Ber_Ses En
En
TIMEOUT_VAL
PLL_FODR
PLL_F
A6 R/W
TIMEOUT VAL[7:0]
A7 R/W Reserved
A8 R/W
OD[1:0]
R[4:0]
F[7:0]
PLL power
down
PLL op
enable
Ext clk
PLL bypass
PLL op
invert
PLL test
mode
Clock
disable
PLL_CONTROL
A9 R/W Reserved
enable
Enable
AF R/W
i2c FET
enable
TUNER_CTRL_5
AUTO_RESET
Reserved
quiet i2c
B1 R/W
Reserved
disable
RF/IF
RF/IF
B2 R/W RF/IF AGCQ PWM[1:0] Reserved IF AGC EN
RF/IF AGCQ MODE
RESET
AGCQ GPO AGCQ GPI
RF_IFAGC_CTRL
SMOOTH_CTRL
B3 R/W
RF/IF AGCQ PWM[9:2]
DATA
PERIOD
AUTO
B4 R/W CHANNEL WIDTH[1:0]
Reserved
ENABLE
UNDER
FLOW
OVER
FLOW
SMOOTH_STAT
SMOOTH_DELAY
B5 R/W
Reserved
B6 R/W
DELAY[7:0]
B7 R/W
DATA_PERIOD[7:0]
SMOOTH_DP
B8 R/W
DATA_PERIOD[15:8]
ADC_CONTROL
ADC_CONTROL2
B9 R/W Reserved Reserved
RST_Q
Reserved Reserved Reserved
RST_I
Reserved
Ext A/D ADC Offset ADC test
Select
BA R/W
BC R/W
REFSEL
DCCEN CLKRCVEN Reserved
2s Comp
mode
RAM_
STAND BY
RAM_CONTROL
Reserved
ADC_CONTROL3
ADC_STATUS
BD R/W RINTEN_Q
BE OVF_Q
RINTSEL_Q[2:0]
OVF_I UDF_I
RINTEN_ I
RINTSEL_I[2:0]
Reserved
R
UDF_Q
- 48 -
SONY [ SONY CORPORATION ]
