CXD1968AR
CXD1968AR COFDM Demodulator Core Registers
COR_CTL
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0x00
Bit
Name
Description
7:6 Reserved
00
R/W
Set to enable core operation. When “0” the core reverts to
and is held in its IDLE mode. This bit will be the normal
method of core enable and disable.
5
4
Core Active
Hold
0
R/W
Set to prevent the state machine from changing state.
For debugging only.
0
R/W
R/W
Core state override
control, when a non-zero
value is written into these
0000: State machine not forced
bits the core state
0001: WAIT_TRL
machine is forced into a
0010: WAIT_AGC
specific state as listed.
0011: WAIT_SYR
3:0 Core State
This field is for debugging
0100: WAIT_PPM
0000
only and not expected to
0101: WAIT_TPS
be used in normal
0110: MONITOR _TPS
operation. In particular
0111 to 1111: Reserved
backward transitions may
give rise to unpredictable
behavior.
COR_STAT
Read Only
Offset Address: 0x01
Bit
7
Name
Description
Default R/W
CHC Tracking
Set when CHC enters tracking state.
—
R
Set when “acceptable” TPS data has been received. This
depends on a good TPS BCH check (TPS_BCHOK) unless
TPS_CTL (TPS Ignore BCH) is set – this differentiates TPS
locked from TPS_RCVD_1 (TPSBCHOK). Cleared when the
state machine is forced back into the IDLE state.
6
TPS Locked
—
R
Set when SYR is locked (guard interval and symbol position
determined).
5
4
SYR Locked
AGC Locked
—
—
R
R
Set when the AGC is locked.
0000: IDLE
0001: WAIT_TRL
0010: WAIT_AGC
0011: WAIT_SYR
Current core state
0100: WAIT_PPM
3:0 Core State
—
R
0101: WAIT_TPS
0110: MONITOR _TPS
0111 to 1111: Reserved
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SONY [ SONY CORPORATION ]
