CXD1968AR
COR_INTEN
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0x02
Bit
7
Name
Description
INTEN Global
Reserved
Set to enable interrupts COR_INTEN[5:0].
0
0
0
R/W
R/W
R/W
6
5
INTEN SYR SymEnd
Set to enable an interrupt on SYR symbol end.
Set to enable an interrupt on completion of FFT
processing.
4
3
INTEN FFT Done
0
0
R/W
R/W
INTEN AGC Lock Change
Set to enable an interrupt on change of AGC lock.
Set to enable an interrupt on receipt of a TPS block
with bad BCH check. This interrupt is NOT
influenced by the TPS_CTL (TPS Use BCH)
register setting.
2
1
0
INTEN TPS RCVD BCHBad
INTEN TPS RCVD Changed
INTEN TPS RCVD Update
0
0
0
R/W
R/W
R/W
Set to enable an interrupt on a change of TPS data
(except frame number). This interrupt indicates
that the contents of the TPS_RCVD_2, 3, 4
registers have changed, this only occurs at the end
of a frame.
Set to enable an interrupt on receipt of a TPS
block. This interrupt indicates that the
TPS_RCVD_1, 2, 3, 4 registers have been
updated, this only occurs at the end of a frame.
COR_INTSTAT
Read/Write
Description
RESET: 0x00
Default R/W
Offset Address: 0x03
Bit
Name
7:6 Reserved
00
0
R/W
R/W
R/W
R/W
Interrupt on SYR symbol
end.
5
4
3
INTSTAT SYR SymEnd
INTSTAT FFT Done
Interrupt on FFT complete.
0
Interrupt on change of
AGC lock.
INTSTAT AGC Lock Change
0
Write a “1” to the
Interrupt on receipt of a
appropriate bit to
2
INTSTAT TPS BCHBad
TPS block with bad BCH
clear the interrupt
0
R/W
check.
flag.
Interrupt on a change of
1
0
INTSTAT TPS RCVD Changed TPS data (except frame
number).
0
0
R/W
R/W
Interrupt on receipt of a
INTSTAT TPS RCVD Update
TPS block.
- 50 -
SONY [ SONY CORPORATION ]
