CXD1968AR
COR_MODEGUARD
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0x04
Bit
7
Name
Description
If set, Zero IF interface is enabled. The core expects the
presence of both I and Q channels.
ZIF_ENABLE
0
R/W
R/W
6:4 Reserved
000
If set, this forces the core to use
the set mode and guard. The core
will not attempt to lock to any
other mode and guard even if they
are set incorrectly.
3
2
Force
Mode
0
0
R/W
R/W
Sets the mode for which the core
attempts lock. Only applicable if
0: Mode = 2K
Force = 1. If the mode is known
1: Mode = 8K
then setting the mode here will
reduce lock times.
Sets the guard interval for which
the core attempts initial lock. If this
00: Guard interval = 1/32
is set incorrectly then the core will
01: Guard interval = 1/16
1:0 Guard
still automatically recover the
10: Guard interval = 1/8
00
R/W
correct guard. If the guard is
11: Guard interval = 1/4
known then setting the guard here
will reduce lock times.
AGC_CTL
Read/Write
Description
RESET: 0x08
Default R/W
Offset Address: 0x05
Bit
Name
Once the AGC has locked, the core begins acquisition.
Setting these bits allows this to be delayed. The length of
time delayed is DelayStartup × 4 symbols (in 8K mode) or
DelayStartup × 16 symbols (in 2K mode). For example a
value of DelayStartup = 3 will delay the acquisition by
~11ms in with a 1/32 guard (i.e. 12 8K-symbols or
48 2K-symbols).
7:5 Delay Startup
000
R/W
After the COR_CTL (Core Active) bit has been set, then a
value of zero in this bit will cause the AGC to start at mid
range and the DAGC to start at a gain of “1”. In this
instance it is necessary to wait for the external RC to settle.
If this bit is set then the AGC and DAGC will retain their last
gain settings which is useful for reducing lock times for
reacquisition after loss of lock.
4
AGC Use Last Value
0
R/W
R/W
00: No reduction
When the AGC loop
01: Reduce BW by 2
locks the BW of the loop
3:2 AGCBW Reduction
10
10: Reduce BW by 4 (Default) is reduced by the
11: Reduce BW by 8 following factors.
When set, the AGC level output decreases when a larger
signal is required, otherwise the AGC level output
increases when a larger signal is required.
1
0
AGC Neg
AGC Set
0
0
R/W
R/W
When set, the AGC output gain control value is set to AGC
Manual. The AGC continues to monitor the received signal
level.
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SONY [ SONY CORPORATION ]
