CXD1968AR
Name
SYR_MISC5
Addr. R/W
5C R/W
7
6
5
4
3
2
1
0
Post echo
ext enable
Echo
stretch
Skirtrmv
Numsymsftrack_lut[2:0]
Nttrack chc FFT 512
AGC_MOD_TARGET_Q
AGC_GAIN_3
AGC_GAIN_4
QIC_MISC1
QIC_IQPHASEERR
TRL_NOMINALRATE_0
CHC_LEAKAGE
TEST1
5F
60
61
R
R
R
AGC_modified_target_q[7:0]
Agc_gain_q[7:0]
Reserved
Reserved
Agc_gain_q[11:8]
QIC Gain[2:0]
62 R/W
63
QIC Enable
IQPhaseErr[7:0]
R
65 R/W
6B R/W
6C R/W
6D R/W
trlnominalrate_0[7:0]
Reserved
Reserved
CHC_LEAKAGE[3:0]
TEST3[4:0]
Reserved
TEST1[0]
TEST2
TEST2[7:0]
TEST3
70 R/W TEST3[7]
TEST4
71
72
73
R
R
R
TEST4[7:0]
TEST5[7:0]
TEST6[7:0]
TEST7[7:0]
TEST8[7:0]
TEST5
TEST6
TEST7
74 R/W
TEST8
75 R/W
AUTORCV_1
AUTORCV_2
76 R/W Reserved
Prescale_Val[6:0]
77 R/W
78 R/W
79 R/W
Activate
Scanning
XMS_Tuner_Wait[1:0]
Reserved
Demod_Timeout_2K[3:0]
CSF_
Enable
CSF_MISC
AUTORCV_3
Reserved
TS_Lock_Timeout[4:0]
Demod_Status[3:0]
AUTORCV_4
7A
7B
7C
7D
7E
R
R
R
R
R
Autorcv_Reserved[3:0]
TPS_RESERVED_1_EVEN
TPS_RESERVED_2_EVEN
DCC_OFFSET_I
TPS_Reserved_Even[7:0]
TPS_Reserved_Even[13:8]
Reserved
DCC_Offset_I[7:0]
DCC_Offset_Q[7:0]
DCC_OFFSET_Q
DCC_
Enable
DCC_MISC
7F R/W
Reserved
DCC_Gain[1:0]
FEC Registers
FEC_PARAMS
Ser data on TS parallel Output Sel Measurement Tri State
80 R/W Tsclk cont Auto clear
Rs Disable
Tsclk full
msb
sel
Msb
Sel
Outputs
Tsvalid
Active High Active High
Tssync TserrActive Latch on
TSsync
byte
BB_PARAMS
BER_PERIOD
FEC_STATUS
81 R/W
83 R/W
Tsclk _204
Tserr full
High
posedge
Berest test
mode
Reserved
Ber Est Period[4:0]
Ts Synch
Lock
84
R
Ber_ses
Ber_es
Lck Flag Ts Llck Flag
Vtb Sync New Ber es Reserved
Synch Lddr Lngth[2:0]
Synch Cntr Ts Synch
SET_SYNC_DETECT
86 R/W
87 R/W
Sync Loss Lddr Length[2:0]
Mode
Cntr Mode
LT_QLTY_THRESHOLD
LT QLTY THRESHOLD[7:0]
BERCNT[7:0]
88
89
R
R
BERCNT[15:8]
BER_ESTIMATE
New
Estimate
BERCNT
overflow
8A
R
Reserved
BERCNT[19:16]
8B
8C
R
R
CWRJCT CNT[7:0]
CWRJCT CNT[15:8]
CWRJCT_CNT
VIT_CTRL
VIT_SN
90 R/W Rate Sel
91 R/W
Rate[2:0]
Reserved
Bert[2:0]
SN[9:5]
Reserved
Reserved
VIT_ST
92 R/W
ST[12:9]
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