CXA3106Q
Control Circuit (3-bit address, 8-bit data)
The timing and input methods are described hereafter.
Feedback programmable counter control
VCO rear-end counter control
REGISTER1, 2 12bit
REGISTER3
REGISTER4
REGISTER4
REGISTER5
REGISTER5
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER6
REGISTER7
REGISTER7
REGISTER7
REGISTER7
2bit
5bit
2bit
2bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
1bit
Fine delay line control
Coarse delay line control
Charge pump current DAC control
Phase detector input positive/negative polarity control
Sync input positive/negative polarity control
Delay sync output positive/negative polarity control
Clock TTL output OFF function
Inverted clock TTL output OFF function
1/2 clock TTL output OFF function
Inverted 1/2 clock TTL output OFF function
Delay sync TTL output OFF function
UNLOCK output OFF function
Programmable counter input switching
Power save with register contents held
Register read function power ON/OFF
Programmable counter TTL output OFF function
Power Save
The CXA3106Q realizes 2-step power saving (all OFF, control registers only ON). This is controlled by a
control register and the chip selector.
Step 1: Chip selector control
L
H
CS
Power save status
All OFF
Power ON
Step 2: Control register control
0
1
Register: Synth power
Power save status
Control registers only ON
Power ON
Readout Circuit (during test mode)
The control register contents can be read by serial data from SEROUT.
(See the Control Register Timing Chart.)
Register: Read out power
Readout status
1
0
Function OFF
Function ON
– 18 –
SONY [ SONY CORPORATION ]
