CXA3106Q
Feedback Programmable Counter
This counter can be set as desired from 256 to 4096 using 12 bits.
Frequency divisions = (m + 1) × 8 + n, n: 3 bits (VCO DIV bits 0 to 2), m: 9 bits (VCO DIV bits 3 to 11)
When the register value is changed, the new setting is actually loaded to the counter when the counter value
becomes "all 0".
Clock Output
When SYNC input is positive polarity, the clock is regenerated in synchronization with the rising edge of the
sync signal.
The clock output delay time can be changed in the range of 1/16 to 20/16 CLK using 5 bits of control register.
(See the I/O Timing Chart.)
Output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL
output can also be turned off independently.
0
1
Register: Clock Enable
Clock output status
OFF
ON
1/2 Clock Output
Reset is performed at the delay sync timing and the clock output is frequency divided by 1/2. (See the I/O
Timing Chart.)
Both odd and even output are TTL and PECL output. TTL output can also be turned off independently.
0
1
Register: Clock Enable
Clock output status
OFF
ON
Delay Sync Output
The front edge of the delay sync pulse is latched by the pulse obtained by frequency dividing the CLK
regenerated by the PLL, so there is almost no jitter with respect to CLK. This front edge can be used as the
reset signal for the system timing circuit.
The rear edge of the delay sync pulse is latched by the CLK regenerated by the PLL. This relationship is
undefined for one clock as shown in the Timing Chart.
The delay sync output delay time can be varied in two stages. First, the delay time can be varied in the range
of 1/16 to 20/16 CLK using 5 bits of control register, and then in the range of 1 to 4 CLK using 2 bits of
control register. In other words, the total delay time is ((1/16 to 20/16) + (1 to 4)) CLK. (See the I/O Timing
Chart.)
DSYNC output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock
TTL output can also be turned off.
0
1
Register: Clock Enable
Clock output status
OFF
ON
Lower delay line
FINE DELAY bits 0 to 4
00000
00001
· · · · · · · · · · · ·
· · · · · · · · · · · ·
10011
Delay time
2/16CLK
20/16CLK
1/16CLK
Upper delay line
COARSE DELAY bits 0 to 1
00
01
10
11
Delay time
2CLK
3CLK
4CLK
1CLK
0
1
Register: DSYNC POL
DSYNC output polarity
Negative
Positive
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SONY [ SONY CORPORATION ]
