CXA3106Q
The settings of the frequency divider (2 bits, DIV1, 2, 4) and programmable counter (12 bits, VCODIV) at the
rear end of the VCO are transferred in the order shown below. (The data will be set when the three registers
are transferred.)
First DIVREG2, CENFREREG and DIVREG1 are set, and then the data is transferred independently at the
timings shown below.
DIVREG2 (upper 4 bits of VCODIV)
↓
CENFREREG (2 bits of DIV1, 2, 4)
↓
DIVREG1 (lower 8 bits of VCODIV)
All three of the above registers must be changed even when changing only (2 bits of DIV1, 2, 4). This is the
same when changing only (12 bits of VCODIV).
SENABLE
SDATA
SCLK
DIVREG2
CENFREREG
DIVREG1
– 21 –
SONY [ SONY CORPORATION ]
