CXA3106Q
Control Register Timing
1) Write mode
Many CXA3106Q functions can be controlled via a program. Characteristics are changed by setting the
internal control register values via a serial interface comprised of three pins: SENABLE (Pin 10), SCLK (Pin
11) and SDATA (Pin 12). The write timing diagram is shown below.
Input the 8-bit data and 3-bit register address MSB first to the SDATA pin. Some registers are not 8 bits, but
the data is input aligned with the LSB side in these cases. (See the Register Table.)
SENABLE is the enable signal and is active low. SCLK is the transfer clock signal, and data is loaded to the
IC at the rising edge. When SENABLE rises, SCLK must be high. (Registers are set at the rising edge of
SENABLE.) When SENABLE falls, SCLK may be either high or low.
SENABLE
8bit
3bit
SDATA
SCLK
DATA
ADDRESS
Enlarged
Enlarged
TENH
TENS
SENABLE
SDATA
SCLK
TDS TDH
For example, when inputting a 16-bit signal, the initial 5 bits are invalid and the latter 11 bits are valid. This is
to say that the latter 11 bits are loaded to the register.
SENABLE
5bit
8bit
3bit
Invalid DATA
address
SDATA
SCLK
DATA
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