CXA3106Q
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
CLK (CLK, CLK/2) output
CLK output (PECL)
frequency range 1
Fclk1PECL DIV = 1/1
Fclk2PECL DIV = 1/2
Fclk3PECL DIV = 1/4
40
20
120
60
MHz
MHz
MHz
ns
CLK output (PECL)
frequency range 2
CLK output (PECL)
frequency range 3
10
30
CLK, CLK/2 output (PECL)
rise time
10% to 90%,
RL = 330Ω
TrPECL
TfPECL
1.0
1.0
40
1.5
1.5
2.0
2.0
80
CLK, CLK/2 output (PECL)
fall time
10% to 90%,
RL = 330Ω
ns
CLK output (TTL)
frequency range 1
Fclk1TTL DIV = 1/1
Fclk2TTL DIV = 1/2
Fclk3TTL DIV = 1/4
MHz
MHz
MHz
ns
CLK output (TTL)
frequency range 2
20
60
CLK output (TTL)
frequency range 3
10
30
CLK, CLK/2 output (TTL)
rise time
10% to 90%,
CL = 10pF
TrTTL
TfTTL
Dclk2
2.0
2.0
40
3.0
3.0
50
4.0
4.0
60
CLK, CLK/2 output (TTL)
fall time
10% to 90%,
CL = 10pF
ns
CLK output (PECL, TTL)
duty
CL = 10pF
CL = 10pF
%
SYNC input (PECL) and
CLK output (PECL) delay Td3
offset
1
ns
ns
ns
ns
ns
ns
CLK output (PECL) and
DSYNC output (PECL)
phase difference
Td4
Td5
CL = 10pF
CL = 10pF
CL = 10pF
CL = 10pF
CL = 10pF
1.5
0.0
2.4
0.8
14
3.0
1.0
CLK output (PECL) and
CLK/2 output (PECL)
phase difference
CLK output (PECL) and
DIVOUT output (TTL) rise Td6
phase difference
CLK output (PECL) and
DIVOUT output (TTL) fall
phase difference
Td7
Td8
11
DSYNC, CLK, CLK/2 PECL
output and TTL output
phase difference
1.5
3.0
4.5
– 14 –
SONY [ SONY CORPORATION ]
