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CXA3106Q 参数 Datasheet PDF下载

CXA3106Q图片预览
型号: CXA3106Q
PDF下载: 下载PDF文件 查看货源
内容描述: PLL IC为液晶显示器/投影仪 [PLL IC for LCD Monitor/Projector]
分类和应用: 显示器
文件页数/大小: 50 页 / 957 K
品牌: SONY [ SONY CORPORATION ]
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CXA3106Q  
Description of Block Diagram  
Sync Input  
Sync signals in the range of 10 to 100kHz can be input. Input supports both positive and negative polarity.  
PECL input can also be a single input.  
When SYNC is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal.  
When SYNC is negative polarity, the clock is regenerated in synchronization with the falling edge of the sync signal.  
VCO oscillation stops when there is no sync input.  
0
1
Register: SYNC POL  
SYNC input polarity  
Negative  
Positive  
Phase Detector  
The phase detector operates at the sync input frequency of 10 to 100kHz. The PD input polarity should be  
set to the default PD POL = 1. Phase comparison is performed at the edges.  
The input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped  
at the front end of the CXA3106Q when inputting a noisy signal.  
The phase detector HOLD signal is supplied by TTL. (See the HOLD Timing Chart.)  
The PLL UNLOCK signal is output by an open collector.  
(See the UNLOCK Timing Chart.)  
Charge Pump  
The gain (I, I/4, I/16) can be varied by changing the charge pump current using 2 bits of control register.  
0
0
Register: C.Pump bit 1  
Register: C.Pump bit 0  
Charge pump current  
1
0
1
1
400µA  
1600µA  
100µA  
LPF  
This is a loop filter comprised of the external capacitors and resistor.  
Be sure to use metal film resistors with little temperature variation and a temperature-compensated capacitor.  
In particular, the 0.33µF capacitor should be equivalent to Murata's high dielectric constant series capacitor  
type B or better. (electrostatic capacitance change ratio ±10%: T = –25 to +85°C)  
VCO  
The VCO oscillator frequency covers from 40 to 120MHz.  
VCO Rear-end Counter  
The VCO output is frequency divided to 1/1, 1/2 or 1/4 by switching 2 bits of control register.  
The operating range can be expanded to 10 to 120MHz by combining the counter with a VCO frequency divider.  
0
0
Register: DIV 1, 2, 4 bit 1  
Register: DIV 1, 2, 4 bit 0  
Counter frequency divisions  
1
0
1
1
1/2  
1/4  
1/1  
– 16 –  
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