CXA3106Q
2) Read mode
Data can be transferred from the shift register to the data register only when SENABLE is high.
Binary data can be read from the data register by inputting SCLK when SENABLE is high. Data is loaded
from the data register to the SCAN PATH circuit each time one clock is input to SCLK, and is output
sequentially from the register read no. 1 data (VCODIV bit 7) through the SEROUT pin. When the 41st SCLK
clock pulse is input, the register read no. 41 data (VCO By-pass) is output. Then, when the 42nd clock pulse
is input to SCLK, the output returns to the register read no. 1 data (VCODIV bit 7) and the data output is
repeated. Also, the data output from the SCAN PATH circuit is automatically reloaded even when the shift
register data is changed during data output.
Note) Since all registers do not have 8 bits, only the valid bits of each register are loaded to the SCAN PATH
circuit. (See the Control Register Table for the actual register read no.)
SCLK
CLK
NEN
I/P SHIFT REGISTER, 11 BITS
8 BIT DATA 3 BIT ADDRESS
7 DATA REGISTERS (41 LATCHES).
REGISTERS ARE DIFFERENT LENGTHS
UP TO 8 BIT
TR
SENABLE
EN
SEROUT
CLK
SCAN PATH, 1 ELEMENT PER REGISTER BIT
Block Diagram during Read Mode
TNENS
TNENH
SENA
READ NO. 1
READ NO. 2
2
READ NO. N
SEROUT
1
N
SCLK
Timing Chart during Read Mode
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SONY [ SONY CORPORATION ]
