EP2_CTL
(0xB4 - RESET=0x00)
ENDPOINT 2 CONTROL REGISTER
DESCRIPTION
BIT
NAME
R/W
4
RAMRD_
TOGGLE
W
Writing a “0” to this bit will begin the output of the 512 byte
SRAM A buffer to either the SIE or the ATA interface,
depending on the value of the DIR bit in this register, while
writing a “1” will begin outputing of SRAM B buffer. See
Sections 6.4, 6.5, and 6.9 for more information. The
RAMRDBC_A and RAMRDBC_B Registers determine how
many bytes will be output from either the A or B SRAM
buffer, respectively. Writing this bit to a “1” will clear the
RAMRD_B bit in the ISR_0 register, while writing it to “0” will
clear the RAMRD_A bit in that register.
R
Upon reads, this bit will reflect the current or last buffer
being read (1=B, 0=A).
3
2
STALL_
RX
R/W
When set to a “1”, EP2 RX will respond with the STALL
handshake to all tokens. . Either the internal SIE or the user
may set this bit. This bit is only cleared when a SET
FEATURE
ENDPOINT
2RX
CLEAR
or
SET
CONFIGURATION command is received on EP0 from the
host, or by a USB reset.
STALL_TX
R/W
When set to a “1”, EP2 TX will respond with the STALL
handshake to all tokens. . Either the internal SIE or the user
may set this bit. This bit is only cleared when a SET
FEATURE
ENDPOINT
2TX
CLEAR
or
SET
CONFIGURATION command is received on EP0 from the
host, or by a USB reset.
1
0
RAMRD_
TOGVALID
R/W
R
This bit always reads “0”. If this bit is set to a “1” when
writes to this register occur, then the value of bit 4 written to
this register will have effect. If cleared, then the values of bit
4, when this register is written, is ignored.
ENABLE
Reads “1” if EP2 is enabled by the SIE in either direction.
Notes:
ꢀ
If the DIR bit is changed, then the RAMWR_TOGGLE bit must be written by the user to assure that the proper
buffer is selected. The user can NOT rely on reading the value of this bit to determine which buffer is active
immediately after changing the DIR bit.
ꢀ
Bit 2, above, will set the STALL condition for both TX and RX directions of EP2. If the host clears the stall in
either direction, then both direction’s STALL condition will be cleared. Bit 3 above will be reserved and always
read a “0”.
Table 36 – Endpoint 0 Receive Byte Count Register
EP0RX_BC
(0xB5 - RESET=0x00)
NAME
ENDPOINT 0 RECEIVE BYTE COUNT REGISTER
DESCRIPTION
BIT
7
R/W
R
Reserved
This bit always reads “0”.
6
64BYTE
R
1 = Indicates that 64 Bytes were received.
[5:0]
COUNT
R
Indicates the byte count of the packet received on EP0 and
stored in SRAM beginning at address 0x0000.
Note: This register is updated at the end of a transfer and is actually the least significant bits of the ending address
in the SRAM buffer.
SMSC DS – USB97C201
Page 34
Rev. 03/25/2002
PRELIMINARY
SMSC [ SMSC CORPORATION ]
