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USB97C201 参数 Datasheet PDF下载

USB97C201图片预览
型号: USB97C201
PDF下载: 下载PDF文件 查看货源
内容描述: USB 2.0的ATA / ATAPI控制器 [USB 2.0 ATA/ ATAPI Controller]
分类和应用: 控制器
文件页数/大小: 59 页 / 377 K
品牌: SMSC [ SMSC CORPORATION ]
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Table 30 – USB Configuration Number Register  
USB_CONF  
(0xAD - RESET=0x00)  
NAME  
USB CONFIGURATION NUMBER REGISTER  
DESCRIPTION  
BIT  
[7:4]  
{3:0}  
R/W  
R
Reserved  
Always returns a “0”.  
CONFIG  
R
Reflects the current configuration number of the  
USB97C201 system as set by the host.  
Table 31 – Endpoint 0 Receive Control Register  
EP0RX_CTL  
(0xAF - RESET=0x00)  
NAME  
ENDPOINT 0 RECEIVE CONTROL REGISTER  
DESCRIPTION  
BIT  
R/W  
[7:4]  
Reserved  
R
This bit always reads “0”.  
3
2
DTOG  
STALL  
R
This bit reflects the data toggle state of the last received  
data token.  
R/W  
When set to a “1”, EP0 will respond with the STALL  
handshake to OUT tokens EXCEPT a SETUP, which it will  
ACK unconditionally. Either the internal SIE or the user may  
set this bit. Receipt of a SETUP packet or USB RESET  
clears this bit. Writing a “0” to this bit has no effect.  
1
0
Reserved  
ENABLE  
R
R
This bit always reads “0”.  
Reads 1 if EP0 Receive is enabled by SIE.  
Table 32 – Endpoint 0 Transmit Control Register  
EP0TX_CTL  
(0xB1 - RESET=0x00)  
NAME  
ENDPOINT 0 TRANSMIT CONTROL REGISTER  
DESCRIPTION  
BIT  
7
R/W  
R
Reserved  
Reserved  
Reserved  
TX  
This bit always reads “0”.  
6
R
This bit always reads “0”.  
5
R
This bit always reads “0”.  
4
R/W  
When written with a “1”, allows the SIE to transfer data from  
the buffer SRAM to EP0. OUT tokens will be NAK’d until the  
transfer has been completed. It is cleared by the SIE when  
transmission of the packet has been completed.  
3
2
Reserved  
STALL  
R
This bit always reads “0”.  
R/W  
When set to a “1”, EP0 TX will respond with the STALL  
handshake to IN tokens. . Either the internal SIE or the user  
may set this bit. Receipt of a SETUP packet or USB RESET  
clears this bit. Writing a “0” to this bit has no effect.  
1
0
Reserved  
ENABLE  
R
R
This bit always reads “0”.  
Reads “1” if EP0 Transmit is enabled by the SIE.  
Table 33 – Endpoint 1 Receive Control Register  
EP1RX_CTL  
(0xB2 - RESET=0x00)  
NAME  
ENDPOINT 1 RECEIVE CONTROL REGISTER  
DESCRIPTION  
BIT  
R/W  
[7:4]  
Reserved  
R
This bit always reads “0”.  
3
2
DTOG  
STALL  
R
This bit reflects the data toggle state of the last received  
data token.  
R/W  
When set to a “1”, EP1 RX will respond with the STALL  
handshake to OUT tokens. . Either the internal SIE or the  
user may set this bit. Receipt of a “CLEAR FEATURE  
ENDPOINT CLEAR” command for this endpoint or USB  
SMSC DS – USB97C201  
Page 32  
Rev. 03/25/2002  
PRELIMINARY  
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