Table 26 - USB Bus Status Register
USB_STAT
(0xAB - RESET=0x00)
NAME
USB BUS STATUS REGISTER
DESCRIPTION
This bit always reads “0”.
BIT
[7]
6
R/W
R
Reserved
EP2_ERR
R/W
1 = Indicates that a token in the opposite direction inferred
by the DIR bit of EP2_CTL register was received, ie an
unexpected IN or OUT token.
5
4
2.0
R/W
R/W
1 = Host is high speed capable. This bit is set if high speed
signaling is received from the host.
USB_RESUME
1 = Indicates that RESUME signaling has been detected.
This is only valid if the USB97C201 is in the SUSPEND
state via bit 0 of the SIE_CONF register.
3
2
USB_RESET
ERROR
R/W
R
1 = Indicates that a USB Reset has been detected.
1 = Indicates that a USB Error has been detected. See the
USB_ERR register for details. This bit is cleared by clearing
the USB_ERR register.
1
0
Reserved
Reserved
R
R
This bit always reads “0”.
This bit always reads “0”.
The bits in this register (except bit 2) are cleared by writing a ‘1’ to the corresponding bit. These bits are ORed, if
unMASKED in the USB_MSK register, and drive a latch for the USB_STAT bit in the ISR_0 register.
Table 27 – USB Bus Status Mask Register
USB_MSK
(0xAC - RESET=0xFF)
NAME
USB BUS STATUS MASK REGISTER
DESCRIPTION
BIT
[7]
6
R/W
R
Reserved
This bit always reads “1”.
EP2_ERR
R/W
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the EP2_ERR bit is set in the USB_STAT
register.
5
4
2.0
R/W
R/W
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the 2.0 bit is set in the USB_STAT register.
USB_RESUME
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the USB_RESUME bit is set in the
USB_STAT register.
3
2
USB_RESET
ERROR
R/W
R/W
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the USB_RESET bit is set in the USB_STAT
register.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the ERROR bit is set in the USB_STAT
register.
1
0
Reserved
Reserved
R
R
This bit always reads “1”.
This bit always reads “1”.
Note1: The mask bits do not prevent the status in the USB_STAT register from being set, only from setting the
USB_STAT bit in the ISR_0 register.
SMSC DS – USB97C201
Page 30
Rev. 03/25/2002
PRELIMINARY
SMSC [ SMSC CORPORATION ]
