USB_ERR
(0xDA - RESET=0x00)
NAME
USB ERROR REGISTER
DESCRIPTION
BIT
R/W
has been received on an endpoint.
Note: Writing a “1” to a bit in this register will clear the bit.. If any bit is set in this register the USB_ERR bit is set in
the USB_STAT register.
Table 51 – MSB ATA Data Register
MSB_ATA
(0xDB - RESET=0x00)
NAME
MSB ATA CONTROL/STATUS DATA REGISTER
DESCRIPTION
BIT
R/W
[7:0]
D[15:8]
R/W
During 8051 writes to XDATA 0x31F0 (the ATA Drives
Control/Status register), data in this register represents the
MS byte of the 16 bit operation to this address. For a read
of 0x31F0, the MS byte data is returned in this register after
the PIO_COMPLETE bit is set in the ATA_CTL register. (the
data returned from the actual read of 31F0 should be
discarded)
Table 52 – LSB ATA Data Register
LSB_ATA
(0xDC - RESET=0x00)
NAME
LSB ATA CONTROL/STATUS DATA REGISTER
BIT
R/W
DESCRIPTION
[7:0]
D[7:0]
R/W
During 8051 reads to XDATA 0x31F1-7 and 33F6 (the ATA
Drive’s 8 bit registers), the actual data is returned in this
register after the PIO_COMPLETE bit is set in the ATA_CTL
register. During writes, this register is unused.
For 8051 read to XDATA 0x31F0, the LS byte of data is
returned in this register after the PIO_COMPLETE bit is set
in the ATA_CTL register. During writes, this register is
unused.
Table 53 – ATA Transfer Count Register 0
ATA_CNT0
(0xE1 - RESET=0x00)
ATA TRANSFER COUNT REGISTER 0
DESCRIPTION
BIT
NAME
R/W
[7:0]
D[7:0]
R/W
See note below.
Table 54 – ATA Transfer Count Register 1
ATA_CNT1
(0xE2 - RESET=0x00)
NAME
ATA TRANSFER COUNT REGISTER 1
DESCRIPTION
BIT
R/W
[7:0]
D[15:8]
R/W
See note below.
Table 55 – ATA Transfer Count Register 2
ATA_CNT2
(0xE3 - RESET=0x00)
NAME
ATA TRANSFER COUNT REGISTER 2
DESCRIPTION
BIT
R/W
[7:0]
D[23:16]
R/W
See note below.
SMSC DS – USB97C201
Page 38
Rev. 03/25/2002
PRELIMINARY
SMSC [ SMSC CORPORATION ]
