Table 28 – SIE Status Register
SIE STATUS REGISTER
SIE_STAT
(0xB0 - RESET=0x00)
NAME
BIT
R/W
DESCRIPTION
[7]
SET_STALL
R/W
Set to “1” if a SET_FEATURE_ENDPOINT_HALT command
is received on any endpoint by the SIE. Which endpoint is
STALLed can be determined by examining their CTL
registers.
6
5
CLR_STALL
SET_CONF
R/W
R/W
Set to “1” if a CLEAR_FEATURE_ENDPOINT_HALT
command is received on any endpoint by the SIE. Which
endpoint’s STALL condition is cleared can be determined
by examining their CTL registers.
Set to “1” if a SET_CONFIGURATION command is received
on endpoint 0 by the SIE and the resulting configuration is
set and reported in the USB_CONFIG register.
4
3
Reserved
SET_INTF
R
This read only bit always returns the value of “0”.
R/W
Set to “1” if a SET_INTERFACE command is received on
endpoint 0 by the SIE.
2
1
Reserved
R-
This read only bit always returns the value of “0”.
SET_REMWU
R/W
Set to “1” if
command is received on endpoint 0 by the SIE.
Set to “1” if
a SET_FEATURE_REMOTE_WAKE_UP
0
CLR_REMWU
R/W
a
CLEAR_FEATURE_ENDPOINT_REMOTE_WAKE_UP
command is received on endpoint 0 by the SIE.
Note: These bits are masked by the SIE_MSK register and OR’d to drive the INT3 interrupt line into the 8051 core.
They may be cleared writing a “1” to the bit location.
Table 29 – SIE Status Mask Register
SIE_MSK
(0xAE - RESET=0xFF)
NAME
SIE STATUS MASK REGISTER
DESCRIPTION
BIT
R/W
[7]
SET_STALL
R/W
1= Disable interrupt generation.
0= Enable interrupt generation.
1= Disable interrupt generation.
0= Enable interrupt generation.
1= Disable interrupt generation.
0= Enable interrupt generation.
This read only bit always returns the value of “1”.
1= Disable interrupt generation.
0= Enable interrupt generation.
This read only bit always returns the value of “1”.
1= Disable interrupt generation.
0= Enable interrupt generation.
1= Disable interrupt generation.
0= Enable interrupt generation.
6
5
CLR_STALL
SET_CONF
R/W
R/W
4
3
Reserved
SET_INTF
R
R/W
2
1
Reserved
R
SET_REMWU
R/W
0
CLR_REMWU
R/W
Note: The mask bits do not prevent the status in the SIE_STAT register from being set, only from driving the INT3
line of the 8051 core high.
SMSC DS – USB97C201
Page 31
Rev. 03/25/2002
PRELIMINARY
SMSC [ SMSC CORPORATION ]
