REG OFFSET
(hex)
NAME
SMI_STS6
DESCRIPTION
15
SMI Status Register 6
This register is used to read the status of the SMI inputs.
Default = 0x00
on VTR POR
(R/W)
The following bits are cleared on a write of ‘1’.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
SMI_EN1
16
SMI Enable Register 1
This register is used to enable the different interrupt sources onto
the group nSMI output.
1=Enable
Default = 0x00
on VTR POR
(R/W)
0=Disable
Bit[0] Reserved
Bit[1] EN_PINT
Bit[2] EN_U2INT
Bit[3] EN_U1INT
Bit[4] EN_FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] EN_WDT
SMI Enable Register 2
SMI_EN2
17
This register is used to enable the different interrupt sources onto
the group nSMI output, and the group nSMI output onto the
nIO_SMI GPI/O pinor the serial IRQ stream.
Unless otherwise noted,
1=Enable
Default = 0x00
on VTR POR
(R/W)
0=Disable
Bit[0] EN_MINT
Bit[1] EN_KINT
Bit[2] EN_SMB
Bit[3] EN_RI1#
Bit[4] EN_P12
Bit[5] EN_RI2#
Bit[6] EN_SMI_S
Bit[7] EN_SMI
SMI_EN3
18
SMI Enable Register 3
This register is used to enable the different interrupt sources onto
the group nSMI output.
1=Enable
Default = 0x00
on VTR POR
(R/W)
0=Disable
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] GP60
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP27
SMSC LPC47S45x
Page 167 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
