REG OFFSET
(hex)
NAME
SMI_EN4
DESCRIPTION
19
SMI Enable Register 4
This register is used to enable the different interrupt sources onto
the group nSMI output.
1=Enable
Default = 0x00
on VTR POR
(R/W)
0=Disable
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] FAN_TACH
Bit[6] GP43
Bit[7] GP61
SMI_EN5
1A
SMI Enable Register 5
This register is used to enable the different interrupt sources onto
the group nSMI output.
1=Enable
Default = 0x00
on VTR POR
(R/W)
0=Disable
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
SMI Enable Register 6
SMI_EN6
1B
This register enables the individual SMI sources onto the SMI_ST
bus. When the enable bit is ‘1’ and the SMI source has asserted
an SMI event, the SMI_ST bus is asserted. The SMI_ST bus
cannot be asserted if the enable bit is ‘0’.
Default = 0x00
on VTR POR
(R/W)
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
SMSC LPC47S45x
Page 168 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
