REG OFFSET
(hex)
NAME
PME_EN5
DESCRIPTION
PME Wake Enable Register 5
0E
This register is used to enable individual PME wake sources onto
the IO_PME# wake bus.
Default = 0x00 on
VTR POR
(R/W)
When the PME Wake Enable register bit for a wake source is
active (“1”), if the source asserts a wake event so that the
associated status bit is “1” and the PME_En bit is “1”, the source
will assert the IO_PME# signal.
When the PME Wake Enable register bit for a wake source is
inactive (“0”), the PME Wake Status register will indicate the state
of the wake source but will not assert the IO_PME# signal.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Enable register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
PME_EN6
0F
PME Enable Register 6
This register enables the individual PME sources onto the
PME_ST bus. When the enable bit is ‘1’ and the PME source has
asserted a wake event, the PME_ST bus is asserted. The
PME_ST bus cannot be asserted if the enable bit is ‘0’.
Default = 0x00 on
VTR POR
(R/W)
Bit[0] PINT
Bit[1] U2INT
Bit[2] U1INT
Bit[3] FINT
Bit[4] MINT
Bit[5] KINT
Bit[6] WDT
Bit[7] SMB
SMI_STS1
10
SMI Status Register 1
This register is used to read the status of the SMI inputs.
The following bits must be cleared at their source.
Bit[0] Reserved
Default = 0x02
on VTR POR
(R/W)
Bit 1 is set to ‘1’ on
VCC POR, VTR
POR, PCI Reset and
soft reset
Bit[1] PINT
The parallel port interrupt defults to 1 when the parallel port
activate bit is cleared. When the parallel port is activated, PINT
follows the nACK input.
Bit[2] U2INT
Bit[3] U1INT
Bit[4] FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] WDT
SMSC LPC47S45x
Page 165 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
