REG OFFSET
(hex)
NAME
PME_EN1
DESCRIPTION
PME Wake Enable Register 1
0A
This register is used to enable individual PME wake sources onto
the IO_PME# wake bus.
Default = 0x00 on
VTR POR
(R/W)
When the PME Wake Enable register bit for a wake source is
active (“1”), if the source asserts a wake event so that the
associated status bit is “1” and the PME_En bit is “1”, the source
will assert the IO_PME# signal.
When the PME Wake Enable register bit for a wake source is
inactive (“0”), the PME Wake Status register will indicate the state
of the wake source but will not assert the IO_PME# signal.
Bit[0] P12
Bit[1] P16
Bit[2] RI1#
Bit[3] KBD
Bit[4] MOUSE
Bit[5] SPEKEY (Wake on specific key)
Bit[6] FAN_TACH
Bit[7] RI2#
The PME Wake Enable register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
PME_EN2
0B
PME Wake Enable Register 2
This register is used to enable individual PME wake sources onto
the IO_PME# wake bus.
Default = 0x00 on
VTR POR
(R/W)
When the PME Wake Enable register bit for a wake source is
active (“1”), if the source asserts a wake event so that the
associated status bit is “1” and the PME_En bit is “1”, the source
will assert the IO_PME# signal.
When the PME Wake Enable register bit for a wake source is
inactive (“0”), the PME Wake Status register will indicate the state
of the wake source but will not assert the IO_PME# signal.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Enable register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
SMSC LPC47S45x
Page 163 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
