REG OFFSET
(hex)
NAME
PME_EN3
DESCRIPTION
PME Wake Status Register 3
0C
This register is used to enable individual PME wake sources onto
the IO_PME# wake bus.
Default = 0x00 on
VTR POR
(R/W)
When the PME Wake Enable register bit for a wake source is
active (“1”), if the source asserts a wake event so that the
associated status bit is “1” and the PME_En bit is “1”, the source
will assert the IO_PME# signal.
When the PME Wake Enable register bit for a wake source is
inactive (“0”), the PME Wake Status register will indicate the state
of the wake source but will not assert the IO_PME# signal.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] GP23
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP27
The PME Wake Enable register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
PME_EN4
0D
PME Wake Enable Register 4
This register is used to enable individual PME wake sources onto
the IO_PME# wake bus.
Default = 0x00 on
VTR POR
(R/W)
When the PME Wake Enable register bit for a wake source is
active (“1”), if the source asserts a wake event so that the
associated status bit is “1” and the PME_En bit is “1”, the source
will assert the IO_PME# signal.
When the PME Wake Enable register bit for a wake source is
inactive (“0”), the PME Wake Status register will indicate the state
of the wake source but will not assert the IO_PME# signal.
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP43
Bit[6] GP60
Bit[7] GP61
The PME Wake Enable register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
SMSC LPC47S45x
Page 164 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
