REG OFFSET
(hex)
NAME
PME_STS2
DESCRIPTION
PME Wake Status Register 2
05
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or the
PME_En bit.
Default = 0x00
on VTR POR
(R/W)
If the wake source has asserted a wake event, the associated
PME Wake Status bit will be a “1”.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Status register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME
Wake Status Register has no effect.
PME_STS3
06
PME Wake Status Register 3
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or the
PME_En bit.
Default = 0x00
on VTR POR
(R/W)
If the wake source has asserted a wake event, the associated
PME Wake Status bit will be a “1”.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] GP23
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP27
The PME Wake Status register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME
Wake Status Register has no effect.
PME_STS4
07
PME Wake Status Register 4
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or the
PME_En bit.
Default = 0x00
on VTR POR
(R/W)
If the wake source has asserted a wake event, the associated
PME Wake Status bit will be a “1”.
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP43
Bit[6] GP60
Bit[7] GP61
The PME Wake Status register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME
Wake Status Register has no effect.
SMSC LPC47S45x
Page 161 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
