REG OFFSET
(hex)
NAME
PME_STS5
DESCRIPTION
PME Wake Status Register 5
08
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or the
PME_En bit.
Default = 0x00
on VTR POR
(R/W)
If the wake source has asserted a wake event, the associated
PME Wake Status bit will be a “1”.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Status register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME
Wake Status Register has no effect.
PME_STS6
09
This register indicates the state of the individual PME sources,
independent of the individual source enables or the PME_En bit.
If the PME source has asserted an event, the associated PME
Status bit will be a “1”.
Default = 0x01 on
VTR POR
(R/W)
Bit[0] PINT
The parallel port interrupt defults to 1 when the parallel port
activate bit is cleared. When the parallel port is activated, PINT
follows the nACK input.
Bit 0 is set to ‘1’ on
VCC POR,
VTR POR,
Bit[1] U2INT
Bit[2] U1INT
Bit[3] FINT
Bit[4] MINT
Bit[5] KINT
Bit[6] WDT
Bit[7] SMB
PCI RESET and
SOFT RESET
The PME Status register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME
Status Register has no effect.
SMSC LPC47S45x
Page 162 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
