8.2 Runtime Registers Block Description
Table 80 − Runtime Registers Block Description
Note: Reserved bits return 0 on read.
REG OFFSET
NAME
PME_STS
DESCRIPTION
(hex)
00
Bit[0] PME_Status
= 0 (default)
Default = 0x00
on VTR POR
(R/W)
= 1 Set when The chip would normally assert the IO_PME# signal,
independent of the state of the PME_En bit.
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or PCI
RESET.
Writing a “1” to PME_Status will clear it and cause the The chip to
stop asserting IO_PME#, if enabled. Writing a “0” to PME_Status
has no effect.
PME_EN
02
Bit[0] PME_En
= 0 IO_PME# signal assertion is disabled (default)
= 1 Enables The chip to assert IO_PME# signal
Bit[7:1] Reserved
Default = 0x00
on VTR POR
(R/W)
PME_En is not affected by Vcc POR, SOFT RESET or PCI
RESET
PME_STS1
04
PME Wake Status Register 1
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or the
PME_En bit.
Default = 0x00
on VTR POR
(R/W)
If the wake source has asserted a wake event, the associated
PME Wake Status bit will be a “1”.
Bit[0] P12
Bit[1] P16
Bit[2] RI1#
Bit[3] KBD
Bit[4] MOUSE
Bit[5] SPEKEY (Wake on specific key)
Bit[6] FAN_TACH
Bit[7] RI2#
The PME Wake Status register is not affected by Vcc POR, SOFT
RESET or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME
Wake Status Register has no effect.
SMSC LPC47S45x
Page 160 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
