Table 50 − RTC Divider Selection Bits
OSCILLATOR
FREQUENCY
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
REGISTER A BITS
DV2
0
DV1
0
DV0
0
MODE
Normal Operate
Reset Divider
Normal Operate
Test
0
0
1
0
1
0
0
1
1
1
0
X
Test
1
1
X
Reset Divider
RS3-0
The four rate selection bits select one of 15 taps on the divider chain or disable the divider output. The selected tap
determines rate or frequency of the periodic interrupt. The program may enable or disable the interrupt with the PIE
bit in Register B. Table 51 lists the periodic interrupt rates and equivalent output frequencies that may be chosen
with the RS0-RS3 bits. These four bits are read/write bits that are not affected by VTR POR.
Table 51 − RTC Periodic Interrupt Rates
RATE SELECT
32.768 kHz TIME BASE
PERIOD RATE FREQUENCY
RS3 RS2 RS1 RS0
OF INTERRUPT
OF INTERRUPT
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0.0
3.90625 ms
7.8125 ms
122.070 μs
244.141 μs
488.281 μs
976.562 μs
1.953125 ms
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
256 Hz
128 Hz
8.192 Hz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
125 ms
8 Hz
250 ms
4 Hz
500 ms
2 Hz
Register B
B7
B6
B5
B4
UIE
B3
B2
DM
B1
B0
SET
PIE
AIE
RES
24/12
DSE
SET
When the SET bit is a "0", the update functions normally by advancing the counts once-per-second. When the SET
bit is a "1", an update cycle in progress is aborted and the program may initialize the time and calendar bytes
without an update occurring in the middle of initialization. SET is a read/write bit, which is not modified by VTR
POR or any internal functions.
PIE
The periodic interrupt enable bit is a read/write bit which allows the periodic-interrupt flag (PF) bit in Register C to
cause the IRQB port to be driven low. The program writes a "1" to the PIE bit in order to receive periodic interrupts at
SMSC DS – LPC47S45x
Page 101 of 259
Rev. 07/09/2001
DATASHEET
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