6.10 Serial IRQ
The LPC47S45x supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt
scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
6.10.1 TIMING DIAGRAMS FOR SER_IRQ CYCLE
A)
Start Frame timing with source sampled a low pulse on IRQ1
START FRAME
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
SL
or
H
R
T
S
R
T
S
R
T
S
R
T
H
PCI_CLK
1
START
SER_IRQ
Drive Source
IRQ
Host Controller
None
IRQ1
None
Note: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy
in a synchronous bridge design.
B)
Stop Frame Timing with Host using 17 SER_IRQ sampling period
IRQ14
FRAME
IRQ15
FRAME
IOCHCK#
FRAME
STOP FRAME
NEXT CYCLE
I 2
S
R
T
S
R
T
S
R
T
H
R
T
PCI_CLK
SER_IRQ
1
3
STOP
START
None
IRQ15
None
Host Controller
Driver
Note: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
Note 1: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-around clock of
the Stop Frame.
SER_IRQ Cycle Control
There are two modes of operation for the SER_IRQ Start Frame.
1. Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the
SER_IRQ is Idle. After driving low for one clock the SER_IRQ is immediately tri-stated without at any time
driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between
Stop and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows
the SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time.
Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock
and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total
low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock,
then tri-state.
Any SER_IRQ Device (i.e., The LPC47S45x) which detects any transition on an IRQ/Data line for which it is
responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an
SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle.
SMSC DS – LPC47S45x
Page 105 of 259
Rev. 07/09/2001
DATASHEET
SMSC [ SMSC CORPORATION ]
