High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.7
RX Data FIFO Direct PIO Burst Read Cycle Timing
Please refer to Section 8.4.7, "RX Data FIFO Direct PIO Burst Reads," on page 109 for a functional
description of this mode.
FIFO_SEL
END_SEL
A[2]
tacyc
tacyc
tacyc
tah
tasu
tcsh
nCS, nRD
tadv
tadv
tdoff
tcsdv
tdon
tadv
tdoh
D[31:0]
Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing
Table 15.11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values
SYMBOL
DESCRIPTION
nCS, nRD De-assertion Time
MIN
TYP
MAX
UNITS
t
13
nS
nS
nS
nS
nS
nS
nS
nS
nS
csh
t
t
nCS, nRD Valid to Data Valid
Address Cycle Time
30
csdv
acyc
45
0
t
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
asu
t
40
9
adv
t
0
0
ah
t
don
t
Data Buffer Turn Off Time
doff
doh
t
Data Output Hold Time
0
Note: A RX Data FIFO direct PIO burst read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and
de-asserted in any order.
Note: Fresh data is supplied each time A[2] toggles.
Revision 1.2 (04-08-08)
450
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
