High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.3
Power-On Configuration Strap Valid Timing
This diagram illustrates the configuration strap valid timing requirements in relation to power-on. In
order for valid configuration strap values to be read at power-on, the following timing requirements
must be met.
2.0V
VDD33IO
tcfg
Configuration Straps
Figure 15.3 Power-On Configuration Strap Latching Timing
Table 15.7 Power-On Configuration Strap Latching Timing Values
DESCRIPTION MIN TYP
Configuration strap valid time
SYMBOL
MAX
UNITS
t
15
mS
cfg
Note: Configuration straps must only be pulled high or low. Configuration straps must not be driven
as inputs.
Note: Device configuration straps are also latched as a result of nRST assertion. Refer to Section
15.5.2, "Reset and Configuration Strap Timing," on page 445 and Section 4.2.4, "Configuration
Straps," on page 40 for additional details.
Revision 1.2 (04-08-08)
446
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
