High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.9
TX Data FIFO Direct PIO Write Cycle Timing
Please refer to Section 8.4.9, "TX Data FIFO Direct PIO Writes," on page 111 for a functional
description of this mode.
FIFO_SEL
A[2], END_SEL
tcycle
tah
tasu
tcsl
tcsh
nCS, nWR
D[31:0]
tdsu
tdh
Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing
Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Write Cycle Time
45
32
13
0
nS
nS
nS
nS
nS
nS
nS
cycle
t
nCS, nWER Assertion Time
csl
t
nCS, nWR De-assertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR De-assertion
Data Hold Time
csh
asu
t
t
0
ah
t
7
dsu
t
0
dh
Note: A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de-
asserted in any order.
Revision 1.2 (04-08-08)
452
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
