High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.5
PIO Burst Read Cycle Timing
Please refer to Section 8.4.5, "PIO Burst Reads," on page 107 for a functional description of this mode.
A[x:5], END_SEL
A[4:2]
tacyc
tacyc
tacyc
tah
tasu
tcsh
nCS, nRD
tcsdv
tdon
tadv
tadv
tadv
tdoff
tdoh
D[31:0]
Figure 15.5 PIO Burst Read Cycle Timing
Table 15.9 PIO Burst Read Cycle Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
13
nS
nS
nS
nS
nS
nS
nS
nS
nS
csh
t
t
30
csdv
acyc
45
0
t
Address Setup to nCS, nRD Valid
Address Stable to Data Valid
Address Hold Time
asu
adv
t
40
9
t
0
0
ah
t
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
don
t
doff
doh
t
0
Note: A host PIO burst read cycle begins when both nCS and nRD are asserted. The cycle ends
when either or both nCS and nRD are de-asserted. These signals may be asserted and de-
asserted in any order.
Note: Fresh data is supplied each time A[2] toggles.
Revision 1.2 (04-08-08)
448
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
