High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.10 Microwire Timing
This section specifies the Microwire EEPROM interface timing requirements. Please refer to Section
10.2.3, "Microwire EEPROM," on page 144 for a functional description of this serial interface.
tcsl
EECS
tckcyc
tcklcsl
tckh
tckl
tcshckh
EECLK
tckldis
tdvckh tckhdis
EEDO
EEDI
tdsckh
tdhckh
tdhcsl
tcshdv
EEDI (VERIFY)
Figure 15.10 Microwire Timing
Table 15.14 Microwire Timing Values
DESCRIPTION MIN
SYMBOL
TYP
MAX
UNITS
t
EECLK cycle time
EECLK high time
EECLK low time
1110
550
550
1070
30
1130
570
570
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
ckcyc
t
ckh
t
ckl
t
EECS high before rising edge of EECLK
EECLK falling edge to EECS low
EEDO valid before rising edge of EECLK
EEDO disable after rising edge of EECLK
EEDI setup to rising edge of EECLK
EEDI hold after rising edge of EECLK
EECLK low to EEDO data disable
EEDI valid after EECS high (VERIFY)
EEDI hold after EECS low (VERIFY)
EECS low
cshckh
t
cklcsl
dvckh
t
550
550
90
t
ckhdis
t
dsckh
dhckh
t
0
t
580
ckldis
t
600
cshdv
t
0
dhcsl
t
1070
csl
SMSC LAN9312
453
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
