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LAN9210 参数 Datasheet PDF下载

LAN9210图片预览
型号: LAN9210
PDF下载: 下载PDF文件 查看货源
内容描述: 外形小巧单芯片以太网控制器与HP Auto-MDIX的 [Small Form Factor Single- Chip Ethernet Controller with HP Auto-MDIX]
分类和应用: 控制器以太网
文件页数/大小: 458 页 / 4618 K
品牌: SMSC [ SMSC CORPORATION ]
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface  
Datasheet  
15.6  
Clock Circuit  
The LAN9312 can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator  
(+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left  
unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle  
is 40% minimum, 50% typical and 60% maximum.  
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal  
input/output signals (XI/XO). See Table 15.15 for crystal specifications.  
Table 15.15 LAN9312Crystal Specifications  
PARAMETER  
SYMBOL  
MIN  
NOM  
AT, typ  
Fundamental Mode  
Parallel Resonant Mode  
MAX  
UNITS  
NOTES  
Crystal Cut  
Crystal Oscillation Mode  
Crystal Calibration Mode  
Frequency  
F
-
-
25.000  
-
MHz  
PPM  
PPM  
PPM  
PPM  
pF  
fund  
o
Frequency Tolerance @ 25 C  
Frequency Stability Over Temp  
Frequency Deviation Over Time  
Total Allowable PPM Budget  
Shunt Capacitance  
F
-
+/-50  
Note 15.11  
Note 15.11  
Note 15.12  
Note 15.13  
tol  
F
-
-
+/-50  
temp  
F
-
+/-3 to 5  
-
age  
-
-
7 typ  
20 typ  
-
+/-50  
C
-
-
O
Load Capacitance  
C
-
-
-
pF  
L
Drive Level  
P
0.5  
-
mW  
Ohm  
W
Equivalent Series Resistance  
Operating Temperature Range  
n/a XI Pin Capacitance  
n/a XO Pin Capacitance  
R
-
30  
+70  
-
1
o
0
-
-
C
3 typ  
3 typ  
pF  
pF  
Note 15.14  
Note 15.14  
-
-
Note 15.11 The maximum allowable values for Frequency Tolerance and Frequency Stability are  
application dependant. Since any particular application must meet the IEEE +/-50 PPM  
Total PPM Budget, the combination of these two values must be approximately +/-45 PPM  
(allowing for aging).  
Note 15.12 Frequency Deviation Over Time is also referred to as Aging.  
Note 15.13 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3 as  
+/- 50 PPM.  
Note 15.14 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not  
included in this value. The XO/XI pin and PCB capacitance values are required to  
accurately calculate the value of the two external load capacitors. These two external load  
capacitors determine the accuracy of the 25.000 MHz frequency.  
Revision 1.2 (04-08-08)  
454  
SMSC LAN9312  
DATASHEET  
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