High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.4
PIO Read Cycle Timing
Please refer to Section 8.4.4, "PIO Reads," on page 106 for a functional description of this mode.
A[x:2], END_SEL
tcycle
tah
tasu
tcsl
tcsh
nCS, nRD
D[31:0]
tdoff
tcsdv
tdoh
tdon
Figure 15.4 PIO Read Cycle Timing
Table 15.8 PIO Read Cycle Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Read Cycle Time
45
32
13
nS
nS
nS
nS
nS
nS
nS
nS
nS
cycle
t
nCS, nRD Assertion Time
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address setup to nCS, nRD Valid
Address Hold Time
csl
t
csh
t
30
csdv
t
0
0
0
asu
t
ah
t
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
don
t
9
doff
doh
t
0
Note: A host PIO read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are de-asserted. These signals may be asserted and de-asserted
in any order.
SMSC LAN9312
447
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
