High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.6
RX Data FIFO Direct PIO Read Cycle Timing
Please refer to Section 8.4.6, "RX Data FIFO Direct PIO Reads," on page 108 for a functional
description of this mode.
FIFO_SEL
A[x:2], END_SEL
tcycle
tasu
tah
tcsl
tcsh
nCS, nRD
D[31:0]
tdoff
tcsdv
tdoh
tdon
Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing
Table 15.10 RX Data FIFO Direct PIO Read Cycle Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Read Cycle Time
45
32
13
nS
nS
nS
nS
nS
nS
nS
nS
nS
cycle
t
CS, nRD Assertion Time
csl
t
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
csh
t
30
csdv
t
0
0
0
asu
t
ah
t
don
t
Data Buffer Turn Off Time
9
doff
doh
t
Data Output Hold Time
0
Note: A RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. The cycle
ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
SMSC LAN9312
449
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
