High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.8
PIO Write Cycle Timing
Please refer to Section 8.4.8, "PIO Writes," on page 110 for a functional description of this mode.
A[x:2], END_SEL
tcycle
tah
tasu
tcsl
tcsh
nCS, nWR
D[31:0]
tdsu
tdh
Figure 15.8 PIO Write Cycle Timing
Table 15.12 PIO Write Cycle Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Write Cycle Time
45
32
13
0
nS
nS
nS
nS
nS
nS
nS
cycle
t
nCS, nWR Assertion Time
nCS, nWR De-assertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
csl
t
csh
asu
t
t
0
ah
t
Data Setup to nCS, nWR De-assertion
Data Hold Time
7
dsu
t
0
dh
Note: A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are de-asserted. These signals may be asserted and de-asserted in any
order.
SMSC LAN9312
451
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
