High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
15.5.2
Reset and Configuration Strap Timing
This diagram illustrates the nRST pin timing requirements and its relation to the configuration strap
pins and output drive. Assertion of nRST is not a requirement. However, if used, it must be asserted
for the minimum period specified. Please refer to Section 4.2, "Resets," on page 36 for additional
information.
trstia
nRST
tcss
tcsh
Configuration
Strap Pins
todad
Output Drive
Figure 15.2 nRST Reset Pin Timing
Table 15.6 nRST Reset Pin Timing Values
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
nRST input assertion time
200
200
10
μS
nS
nS
nS
rstia
t
Configuration strap pins setup to nRST deassertion
Configuration strap pins hold after nRST deassertion
Output drive after deassertion
css
csh
t
t
30
odad
Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 4.2.4,
"Configuration Straps," on page 40 for details.
SMSC LAN9312
445
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
