Note 2: If both STA and STO are set high simultaneously in master mode, a STOP condition followed
by a START condition + address will be generated. This allows ‘chaining’ of transmissions without
relinquishing bus control.
Note 3: All other STA and STO mode combinations not mentioned in Table 72 are NOPs.
status bits will be reset to zero on a BER (bus
error) condition.
BIT 0 ACK
This bit must be set normally to logic “1”. This
causes the ACCESS.bus to send an
acknowledge automatically after each byte (this
occurs during the 9th clock pulse) . The bit must
be reset (to logic “0”) when the ACCESS.bus
controller is operating in master/receiver mode
and requires no further data to be sent from the
slave transmitter. This causes
acknowledge on the ACCESS.bus, which halts
further transmission from the slave device.
In polled applications, the PIN bit is tested to
determine when a serial transmission/reception
has been completed. When the ENI bit (bit 4 of
write-only section of register S1) is also set to
logic “1” the hardware interrupt is enabled. In
this case, the PI flag also triggers and internal
interrupt (active low) via the nINT output each
time PIN is reset to logic “0”.
a negative
When acting as a slave transmitter or slave
receiver, while PIN=0, the chip will suspend
ACCESS.bus transmission by holding the SCL
line low until the PIN bit is set to logic “1”
(inactive). This prevents further data from being
transmitted or received until the current data
byte in S0 has been read (when acting as slave
receiver) or the next data byte is written to S0
(when acting as slave transmitter).
Register S1 Status Section
The read-only section of S1 enables access to
ACCESS.bus status information.
BIT 7 PIN
Pending Interrupt Not. This bit is a status flag
which
is
used
to
synchronize
serial
communication and is set to logic “0” whenever
the chip requires servicing. The PIN bit is
normally read in polled applications to
determine when an ACCESS.bus byte
transmission/reception is completed.
PIN bit summary:
·
The PIN bit can be used in polled
applications to test when serial
a
transmission has been completed. When
the ENI bit is also set, the PIN flag sets the
internal interrupt via the nINT output.
Setting the STA bit (start bit) will set PIN=1
(inactive).
In transmitter mode, after successful
transmission of one byte on the
ACCESS.bus the PIN bit will be
automatically reset to logic “0” (active)
indicating a complete byte transmission.
In transmitter mode, PIN is set to logic “1”
(inactive) each time register S0 is written.
In receiver mode, PIN is set to logic “0”
(inactive) on completion of each received
byte. Subsequently, the SCL line will be
held low until PIN is set to logic “1”.
Each time a serial data transmission is initiated
(by setting the STA bit in the same register) the
PIN bit will be set to logic “1” automatically
(inactive). When acting as transmitter, PIN is
also set to logic 1 (inactive) each time S0 is
·
·
written.
In receiver mode, the PIN bit is
automatically set to logic “1” each time the data
register S0 is read.
After transmission or reception of one byte on
the ACCESS.bus (9 clock pulses, including
acknowledge) the PIN bit will be automatically
reset to logic “0” (active) indicating a complete
byte transmission/reception. When the PIN bit
is subsequently set to logic “1” (inactive) all
·
·
165
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