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FDC37CXFR 参数 Datasheet PDF下载

FDC37CXFR图片预览
型号: FDC37CXFR
PDF下载: 下载PDF文件 查看货源
内容描述: 即插即用兼容超I / O控制器,提供快速IR [Plug and Play Compatible Ultra I/O Controller with Fast IR]
分类和应用: 控制器
文件页数/大小: 258 页 / 898 K
品牌: SMSC [ SMSC CORPORATION ]
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SYSTEM MANAGEMENT INTERRUPT (SMI)  
The FDC37C93xFR implements a group nSMI they can be accessed through the Index and  
output pin. The System Management Interrupt  
is a non-maskable interrupt with the highest  
priority level used for transparent power  
management. The nSMI group interrupt output  
consists of the enabled interrupts from each of  
the functional blocks in the chip. The interrupts  
are enabled onto the group nSMI output via the  
SMI Enable Registers 1and 2. The nSMI output  
is then enabled onto the group nSMI output pin  
via bit[7] in the SMI Enable Register 2.  
Data Register.  
SMI Enable Registers  
SMI Enable Register 1  
(Configuration Register B4, Logical Device 8)  
This register is used to enable the different  
interrupt sources onto the group nSMI output.  
SMI Enable Register 2  
(Configuration Register B5, Logical Device 8)  
This register is used to enable additional  
interrupt sources onto the group nSMI output.  
This register is also used to enable the group  
nSMI output onto the nSMI GPI/O pin and the  
routing of 8042 P12 internally to nSMI.  
The logic equation for the nSMI output is as  
follows:  
nSMI = (EN_IDE1 and IRQ_IDE1) or (EN_PINT  
and IRQ_PINT) or (EN_U2INT and  
IRQ_U2INT) or (EN_U1INT and  
IRQ_U1INT)  
or  
(EN_FINT  
and  
IRQ_FINT) or (EN_GPINT2 and  
IRQ_GPINT2) or (EN_GPINT1 and  
IRQ_GPINT1) or (EN_WDT and  
SMI Status Registers  
SMI Status Register 1  
IRQ_WDT)  
IRQ_MINT)  
IRQ_KINT)  
IRQ_IRINT)  
IRQ_BINT)  
IRQ_ABINT)  
or  
or  
or  
or  
or  
(EN_MINT  
(EN_KINT  
(EN_IRINT  
(EN_BINT  
(EN_ABINT  
and  
and  
and  
and  
and  
(Configuration Register B6, Logical Device 8)  
This register is used to read the status of the  
SMI input events. Note: The status bit gets set  
whether or not the interrupt is enabled onto the  
group SMI output.  
SMI Status Register 2  
(Configuration Register B7, Logical Device 8)  
This register is used to read the status of the  
SMI input events. Note: The status bit gets set  
whether or not the interrupt is enabled onto the  
group SMI output.  
REGISTERS  
The following registers can be accessed when in  
configuration mode at Logical Device 8,  
Registers B4-B7 and when not in configuration  
162  
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