Table 73 - ACCESS.BUS Own Address Register S0’
Own
Addr
R/W
D7
R/W
Reserved
D6
R/W
Slave
D5
R/W
Slave
D4
R/W
Slave
D3
R/W
Slave
D2
R/W
Slave
D1
R/W
Slave
D0
R/W
Slave
Bit Def
Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0
In receiver mode the ACCESS.bus data is
shifted into the shift register until the
acknowledge phase. Further reception of data
is inhibited (SCL held low) until the S0 data shift
register is read.
DATA SHIFT REGISTER S0
Register S0 acts as serial shift register and read
buffer interfacing to the ACCESS.bus. All read
and write operations to/from the ACCESS.bus
are done via this register. ACCESS.bus data is
always shifted in or out of shift register S0.
In the transmitter mode data is transmitted to
the ACCESS.bus as soon as it is written to the
S0 shift register if the serial I/O is enabled
(ESO=1).
ACCESS.BUS Data Register
Data
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
167
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