ACCESS.bus block. This determines the SCL
clock frequency generated by the chip. The
selection is made via Bits[2:0] (see Table 74).
CLOCK REGISTER S2
Register S2 controls the selection of the internal
chip
clock
frequency
used
for
the
ACCESS.BUS Clock Register
Clock
R/W
D[7]
R
D[6:3]
R
D[2:0]
R/W
Bit Def
AB_RST
Reserved
See table below
Default = 00 at hard reset and power on reset.
Bit[7]: AB_RST. ACCESS.bus Reset Bit. This
bit resets the entire ACCESS.bus block. Not
self-clearing, must be written high and then
written low.
Table 74 - Internal Clock Rates and ACCESS.bus Data Rates in the FDC37C93xFR
ACCESS BUS CLOCK
REGISTER D[2:0]
NOMINAL NOMINAL
MINIMUM
HIGH
CLOCK RATE DATA RATE
HIGH
LOW
000
001
010
011
100
101
110
Off
12MHz
14.318 MHz
16MHz
50kHz
60kHz
67kHz
100kHz
8ms
6.7ms
6ms
12ms
10.1ms
9ms
4ms
4ms
4ms
4ms
24MHz
4ms
6ms
168
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