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47N350 参数 Datasheet PDF下载

47N350图片预览
型号: 47N350
PDF下载: 下载PDF文件 查看货源
内容描述: LEGACY免费的键盘嵌入式控制器, SPI和LPC接口对接 [LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 346 页 / 4406 K
品牌: SMSC [ SMSC CORPORATION ]
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Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface  
Note: Bits D0 and D2 in the ECI Primary Base Address Low Byte must be “0”. For example, 0x62 is  
a valid ECI Base Address, while 0x66 is not a valid ECI Base Address. The valid ECI Primary  
Base Address range is 0x0000 – 0x0FFA.  
Table 4.1 ECI Configuration Registers (LDN8)  
VCC1 &  
HARD  
SOFT  
VCC2  
POR  
VCC0  
POR  
INDEX TYPE RESET  
RESET  
DESCRIPTION  
D7 D6 D5 D4 D3 D2  
D1  
D0  
0x30  
0x60  
0x61  
R/W  
R/W  
R/W  
0x00  
0x00  
0x62  
0x00  
0x00  
0x62  
0x00  
0x00  
0x62  
-
-
-
ACTIVATE  
Reserved  
Activate  
ECI PRIMARY BASE ADDRESS HIGH BYTE  
“0” “0” “0” “0” A11 A10 A9  
A8  
ECI PRIMARY BASE ADDRESS LOW BYTE (See  
Note 4.1))  
A7 A6 A5 A4  
A3  
“0”  
A1  
“0”  
Note 4.1 Bits D0 and D2 of the ECI Base Address Low Byte must be “0”.  
4.2  
ECI Runtime Registers  
An ACPI-compliant ECI contains three registers: EC_COMMAND, EC_STATUS, and EC_DATA. The  
ECI registers occupy two addresses in the Host I/O space (Table 4.2).  
The EC_DATA and EC_COMMAND registers appear as a single 8-bit data register in the 8051. The  
CMD bit in the EC_STATUS register is used by the 8051 to discriminate commands from data written  
by the host to the ECI. CMD is controlled by hardware: host writes to the EC_DATA register set CMD  
= “0”; host writes to the EC_COMMAND register set CMD = “1”.  
Descriptions of these registers follow in the sections below.  
Table 4.2 ECI Run-Time Registers  
ISA HOST INTERFACE  
8051 INTERFACE  
CMD  
8051  
REGISTER  
HOST  
(Note  
4.2)  
INDEX  
8051  
POWER  
PLANE  
VCC1  
POR  
VCC2  
POR  
NAME  
HOST INDEX  
TYPE  
(7F00+) TYPE  
EC_DATA  
ECI Base Address  
R/W  
W
0
1
-
0x53  
0x53  
0x54  
R/W  
R
VCC1  
-
-
-
-
-
EC_COMMAND  
EC_STATUS  
ECI Base Address + 4  
R
R/W  
0x00  
Note 4.2 CMD is bit D3 in the EC_STATUS register.  
4.3  
EC_STATUS Register  
The EC_STATUS register indicates the state of the Embedded Controller Interface. To the host, the  
EC_STATUS register is read-only. To the 8051, some bits in the EC_STATUS register are read-only  
(Table 4.3). These bits are controlled by hardware. The 8051 software controlled bits in the  
EC_STATUS register are read/write.  
Revision 1.1 (01-14-03)  
SMSC LPC47N350  
DATA2S2HEET