Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 3.4 Example 1: I/O Read, No Wait States (continued)
FIELD
DRIVEN BY
CLOCKS
LAD[3:0]
COMMENT
TAR
Special
1111
Not driven
0000
Sync=0000 (Sync achieved with no error) (See Note
below))
Sync
Data
xxxx
xxxx
1111
First nibble of byte
Second nibble of byte
LPC47N350
Special
1
LPC47N350 drives LAD[3:0] high in 1st half
Not driven
TAR
Note: The actual implementation requires that three wait states (SYNC=0110) precede the SYNC of
0000.
3.1.11.2 EXAMPLE 2: I/O Read, Many Wait States
The I/O transfer is initiated when the host asserts LFRAME# for one or more clocks and drives a start
value onto the LAD[3:0] signals. The following sequence of fields is encoded onto the LAD[3:0] signals
as the transfer proceeds (Table 3.5):
Table 3.5 Example 2: I/O Read, Many Wait States
FIELD
START
DRIVEN BY
CLOCKS
LAD[3:0]
COMMENT
Host
1
0000
000x
xxxx
xxxx
xxxx
xxxx
1111
LAD[3:0]=0000
CYCTYP+DIR
ADDR
LAD[3:2]=00 (I/O cycle), LAD[1]=0 (read)
Most significant nibble
Least significant nibble
TAR
Host drives LAD[3:0] high in 1st half
Not driven
Special
Sync
LPC47N350
0110
Sync=0110 (Sync not achieved yet)
.
.
.
Sync
LPC47N350
1
0110
0000
xxxx
xxxx
1111
Sync=0110 (Sync not achieved yet)
Sync=0000 (Sync achieved with no error)
First nibble of byte
Data
TAR
Second nibble of byte
Peripheral drives LAD[3:0] high in 1st half
Not driven
Special
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA1S9HEET
SMSC [ SMSC CORPORATION ]
