Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
commands to be sent from the host. Burst Mode allows the OS or system management handler to
quickly read and write several bytes of data at a time without the overhead of SCIs between commands.
Note: The BURST bit is maintained by 8051 software, only.
SCI_EVT Bit – D5
The SCI Event flag SCI_EVT is “1” when an SCI event is pending; i.e., the 8051 is requesting an SCI
query; SCI_EVT is “0” when no SCI events are pending.
The SCI_EVT bit is an 8051-maintained software flag that is set when the embedded controller has
detected an internal event that requires operating system attention. The EC sets SCI_EVT before
generating an SCI to the OS.
Note: The SCI_EVT bit is maintained by 8051 software, only.
SMI_EVT Bit – D6
The SMI Event flag SMI_EVT is “1” when an SMI event is pending; i.e., the 8051 is requesting an SMI
query; SMI_EVT is “0” when no SMI events are pending.
The SMI_EVT bit is an 8051-maintained software flag that is set when the embedded controller has
detected an internal event that requires system management interrupt handler attention. The EC sets
SMI_EVT before generating an SMI.
Note: The SMI_EVT bit is maintained by 8051 software, only.
4.4
4.5
EC_COMMAND Register
The EC_COMMAND register is a write-only register that allows the host to issue commands to the
embedded controller.
Writes to the EC_COMMAND register are latched in the 8051 data register and the input buffer full flag
is set in the EC_STATUS register. Writes to the EC_COMMAND register also cause the CMD bit to be
set to “1” in the EC_STATUS register.
EC_DATA Register
The EC_DATA register is a read/write register that allows the host to issue command arguments to the
embedded controller and allows the OS to read data returned by the embedded controller.
Host writes to the EC_DATA register are latched in the 8051 data register and the input buffer full flag
is set in the EC_STATUS register. Host writes to the EC_DATA register also cause the CMD bit to be
reset to “0” in the EC_STATUS register.
Host reads from the EC_DATA register return data from the 8051 data register and clear the output
buffer full flag in the EC_STATUS register.
Revision 1.1 (01-14-03)
SMSC LPC47N350
DATA2S4HEET
SMSC [ SMSC CORPORATION ]
