Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
EXAMPLE 3: I/O Write, No Wait States
The I/O transfer is initiated when the host asserts LFRAME# for one or more clocks and drives a start
value onto the LAD[3:0] signals. The following sequence of fields is encoded onto the LAD[3:0] signals
as the transfer proceeds (Table 3.6):
Table 3.6 Example 3: I/O Write, No Wait States
FIELD
START
DRIVEN BY
CLOCKS
LAD[3:0]
COMMENT
0000
LAD[3:0]=0000
CYCTYP+DI
R
LAD[3:2]=00 (I/O cycle), LAD[1]=1 (write)
001x
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
Most significant nibble
ADDR
Data
Host
Least significant nibble
First nibble of byte
1
Second nibble of byte
Host drives LAD[3:0] high in 1st half
Not driven
TAR
Sync
TAR
1111
0000
1111
Special
Sync=0000 (Sync achieved with no error) (See Note
below)
LPC47N350
LPC47N350
Special
LPC47N350 drives LAD[3:0] high in 1st half
Not driven
Note: The actual implementation requires that two wait states (SYNC=0110) precede the SYNC of
0000.
3.1.12 LPC Power Management
The LPCPD# signal and the CLKRUN# signal (see the the Intel Low Pin Count Specification) are
implemented in the LPC47N350. The LPC47N350 tolerates the LPCPD# signal going active and then
inactive again without LRESET# going active. This is a requirement for notebook power management
functions.
The LPC Bus spec 1.0 section 8.2 states that "After LPCPD# goes back inactive, the LPC I/F will always
be reset using LRST#”. This text must be qualified for mobile systems where it is possible that when
exiting a "light" sleep state (ACPI S1, APM POS), LPCPD# may be asserted but the LPC Bus power
may not be removed, in which case LRESET# will not occur. When exiting a "deeper" sleep state (ACPI
S3-S5, APM STR, STD, soft-off), LRESET# will occur.
The LPCPD# pin is implemented as a “local” powergood for the LPC bus in the LPC47N350. It is not
to be used as a global powergood for the chip. It is used to minimize the LPC power dissipation. It
should be used to reset the LPC block and hold it in reset.
Prior to going to a low-power state, the system asserts the LPCPD# signal. LPCPD# goes active at least
30 microseconds prior to the LCLK signal stopping low and power being shut to the other LPC interface
signals. Upon recognizing LPCPD# active, there are no further transactions on the LPC interface.
Revision 1.1 (01-14-03)
SMSC LPC47N350
DATA2S0HEET
SMSC [ SMSC CORPORATION ]
