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47N350 参数 Datasheet PDF下载

47N350图片预览
型号: 47N350
PDF下载: 下载PDF文件 查看货源
内容描述: LEGACY免费的键盘嵌入式控制器, SPI和LPC接口对接 [LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 346 页 / 4406 K
品牌: SMSC [ SMSC CORPORATION ]
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Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface  
Table 29.3 PS/2 Channel Transmission Timing Parameters (continued)  
PARAMETER  
MIN  
TYP  
MAX  
UNITS  
t13  
t14  
Trailing edge of PS_T/R to XMIT_IDLE bit asserted.  
100  
ns  
DATA released to high-Z following the PS2_T/R bit  
going low.  
t15  
t16  
XMIT_IDLE bit driven high to interrupt generated.  
Note1- Interrupt is cleared by reading the 8051 INT0  
Source Register.  
The PS2 Channel’s CLK and DATA lines are driven to  
the values stored in the WR_CLK and WR_DATA bits of  
the Control Register when PS2_EN is written to 0.  
PS2_CLK1  
PS2_DAT  
note1  
note1  
t1  
t1  
note2  
note2  
Interrupt  
PS2_EN  
Figure 29.15 PS/2 Channel “Bit-Bang” Transmit Timing Diagram  
Table 29.4 PS/2 Channel “Bit-Bang” Transmit Timing Parameters  
PARAMETER  
Falling Edge of CLK to Interrupt generated.  
MIN  
TYP  
MAX  
UNITS  
t1  
1.1  
µs  
Note 29.5 8051 firmware responds to interrupt and drives data line before rising edge of PS2_CLK line.  
Note 29.6 8051 firmware clears Interrupt by reading the 8051 INT0 Source Register.  
PS2_CLK1  
PS2_DAT  
note1  
note1  
t1  
t1  
note2  
note2  
Interrupt  
PS2_EN  
Figure 29.16 PS/2 Channel “Bit-Bang” Receive Timing Diagram  
Table 29.5 PS/2 Channel “Bit-Bang” Receive Timing Parameters  
PARAMETER  
MIN  
TYP  
MAX  
UNITS  
t1  
Falling Edge of CLK to Interrupt  
generated.  
100  
ns  
Revision 1.1 (01-14-03)  
300  
SMSC LPC47N350  
DATASHEET  
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