Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
SPCLK (CLKPOL = 0)
SPCLK (CLKPOL = 1)
SPDOUT
(TCLKPH = 0)
SPDIN
(RCLKPH = 1)
CS (GPIO)
FIRST DATA BIT
LAST DATA BIT
SAMPLED BY MASTER
SAMPLED BY SLAVE
FIRST DATA BIT
SAMPLED BY SLAVE
LAST DATA BIT
SAMPLED BY MASTER
Figure 29.21 SPI Interface Timing, Full Duplex Mode (TCLKPH = 0, RCLKPH = 1)
29.8.3.4 SPI Interface Timing - Full Duplex Mode (TCLKPH = 1, RCLKPH = 1)
In this mode, the master and slave require an initial SPCLK edge before data is available. Data is
sampled on the second and following even SPCLK edges by the master and slave.
SPCLK (CLKPOL = 0)
SPCLK (CLKPOL = 1)
SPDOUT
(TCLKPH = 1)
SPDIN
(RCLKPH = 1)
CS (GPIO)
FIRST DATA BIT
SAMPLED BY MASTER
AND SLAVE
LAST DATA BIT
SAMPLED BY MASTER
AND SLAVE
Figure 29.22 SPI Interface Timing - Full Duplex Mode (TCLKPH = 1, RCLKPH = 1)
Revision 1.1 (01-14-03)
304
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
