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47N350 参数 Datasheet PDF下载

47N350图片预览
型号: 47N350
PDF下载: 下载PDF文件 查看货源
内容描述: LEGACY免费的键盘嵌入式控制器, SPI和LPC接口对接 [LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 346 页 / 4406 K
品牌: SMSC [ SMSC CORPORATION ]
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Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface  
Table 29.2 PS/2 Channel Receive Timing Parameters  
PARAMETER  
MIN  
TYP  
MAX  
UNITS  
t1  
The PS2 Channel’s CLK and DATA lines are  
floated following PS2_EN=1 and PS2_T/R=0.  
100  
ns  
t2  
t3  
t4  
t5  
Period of CLK  
60  
30  
302  
151  
us  
Duration of CLK high (active)  
Duration of CLK low (inactive)  
DATA setup time to falling edge of CLK.  
LPC47N350 samples the data line on the  
falling CLK edge.  
1
2
t6  
t7  
DATA hold time from falling edge of CLK.  
LPC47N350 samples the data line on the  
falling CLK edge.  
Duration of Data Frame. Falling edge of Start  
bit CLK (1st clk) to falling edge of Parity bit  
CLK (10th clk).  
2.002  
ms  
t8  
t9  
Falling edge of 11th CLK to RDATA_RDY  
asserted.  
1.6  
µs  
Trailing edge of the 8051’s RD signal of the  
Receive Register to RDATA_RDY bit  
deasserted.  
100  
ns  
t10  
t11  
Trailing edge of the 8051’s RD signal of the  
Receive Register to the CLK line released to  
high-Z.  
The PS2 Channel’s CLK and DATA lines are  
driven to the values stored in the WR_CLK  
and WR_DATA bits of the Control Register  
when PS2_EN is written to 0.  
t12  
RDATA_RDY asserted to interrupt generated.  
Note1- Interrupt is cleared by reading the  
8051 INT0 Source Register.  
Revision 1.1 (01-14-03)  
298  
SMSC LPC47N350  
DATASHEET  
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